M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 249

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
19.5 Operational Modes
Figure 19.12 Transition between Operational Modes
The CAN module has the following four operational modes.
• CAN reset/Initialization mode
• CAN operation mode
• CAN sleep mode
• CAN interface sleep mode
Figure 19.12 shows the Transition between Operational Modes.
19.5.1 CAN Reset/Initialization Mode
CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit in the CiCTLR
register ( i = 0, 1) to 1. If the Reset bit is set to 1, check that the State_Reset bit in the CiSTR register is set
to 1.
Entering CAN reset/initialization mode initiates the following functions by the module:
• CAN communication is impossible.
• When CAN reset/initialization mode is activated during an ongoing transmission in operation mode,
• Registers CiMCTLj (j = 0 to 15), CiSTR, CiICR, CiIDR, CiRECR, CiTECR, and CiTSR are initialized.
• Registers CiCTLR, CiCONR, CiGMR, CiLMAR, and CiLMBR, and the CANi message box retain their
the module suspends the mode transition until completion of the transmission (successful, arbitration
loss, or error detection). Then, the State_Reset bit is set to 1, and CAN reset/initialization mode is
activated.
All these registers are locked to prevent CPU modification.
contents and are available for CPU access.
CCLK3, CCLK7: Bits in CCLKR register
Reset, Sleep, RetBusOff: Bits in CiCTLR register ( i = 0, 1)
State_Reset, State_BusOff: Bits in CiSTR register
Apr 14, 2006
CAN interface
sleep mode
MCU Reset
page 225 of 376
CCLK3 = 1 or
CCLK3 = 0 or
CCLK7 = 1
CCLK7 = 0
Sleep = 0
CAN reset/initialization
CAN sleep mode
State_Reset = 1
mode
Sleep = 1
Reset = 0
Reset = 1
Reset = 1
TEC > 255
CAN operation mode
State_BusOff = 1
State_Reset = 0
Bus off state
when 11 consecutive
recessive bits are
detected 128 times
or
RetBusOff = 1
19. CAN Module