M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 179

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.12 Transfer Clock Polarity
15.1.1.1 Counter Measure for Communication Error Occurs
15.1.1.2 CLK Polarity Select Function
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
• Resetting the UiRB register (i = 0 to 2)
• Resetting the UiTB register (i = 0 to 2)
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 15.12
shows the Transfer Clock Polarity.
Apr 14, 2006
(1) Set the RE bit in the UiC1 register to 0 (reception disabled)
(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)
(3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to 1 (reception enabled)
(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)
(2) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode)
(3) 1 (transmission enabled) is written to the TE bit in the UiC1 register, regardless of the TE bit
RXDi
i = 0 to 2
* This applies to the case where the UFORM bit in the UiC0 register = 0
NOTES:
(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling
CLKi
CLKi
TXDi
RXDi
TXDi
(2) When the CKPOL bit = 1 (transmit data output at the rising edge and the receive
(LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse).
1. When not transferring, the CLKi pin outputs a high signal.
2. When not transferring, the CLKi pin outputs a low signal.
edge and the receive data taken in at the rising edge of the transfer clock)
data taken in at the falling edge of the transfer clock)
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D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
(NOTE 1)
(NOTE 2)
15. Serial Interface