M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 111

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 10.10 Interrupts Priority Select Circuit
Apr 14, 2006
Timer B4, UART1 bus collision detection
Timer B3, UART0 bus collision detection
SI/O3, CAN1 successful transmission, INT4
Oscillation stop and re-oscillation detection
CAN1 successful reception, INT5
CAN0 successful transmission
UART2 bus collision detection
UART1 transmission, NACK1
UART0 transmission, NACK0
UART2 transmission, NACK2
Priority level of each interrupt
CAN0 successful reception
A/D conversion, Key input
UART1 reception, ACK1
UART2 reception, ACK2
UART0 reception, ACK0
CAN0/1 wake-up
Watchdog timer
Address match
CAN0/1 error
Timer B0
Timer A3
Timer B1
Timer A4
Timer A2
Timer A0
Timer B5
Timer B2
Timer A1
DMA1
DMA0
INT3
I flag
DBC
INT1
INT2
INT0
NMI
IPL
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(initial value)
Level 0
Highest
Lowest
Priority of peripheral function interrupts
(if priority levels are same)
Interrupt request level resolution output to clock generation circuit
(Figure 8.1 Clock Generation Circuit)
Interrupt request accepted
10. Interrupts