M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 115

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
10.10 Address Match Interrupt
Table 10.6 Value of PC that is Saved to Stack Area when Address Match Interrupt Request is Accepted
Value of PC that is saved to stack area: Refer to 10.5.7 Saving Registers.
Table 10.7 Relationship between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Sources Address Match Interrupt Enable Bit
Address match interrupt 0 AIER0
Address match interrupt 1 AIER1
Address match interrupt 2 AIER20
Address match interrupt 3 AIER21
An address match interrupt request is generated immediately before executing the instruction at the
address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi
register. Use bits AIER0 and AIER1 in the AIER register and bits AIER20 and AIER21 in the AIER2 register
to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
For address match interrupts, the value of the PC that is saved to the stack area varies depending on the
instruction being executed (refer to 10.5.7 Saving Registers). (The value of the PC that is saved to the
stack area is not the correct return address.) Therefore, follow one of the methods described below to
return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
Table 10.6 shows the Value of PC that is Saved to Stack Area when Address Match Interrupt Request is
Accepted. Table 10.7 shows the Relationship between Address Match Interrupt Sources and Associated
Registers.
Note that when using the external bus in 8-bit width, no address match interrupts can be used for external
areas.
Figure 10.14 shows Registers AIER, AIER2, and RMAD0 to RMAD3.
• 16-bit operation code instruction
• Instruction shown below among 8-bit operation code instructions
Instructions other than the above
similar other instruction and then use a jump instruction to return.
ADD.B:S
OR.B:S
STNZ.B:S
CMP.B:S
JMPS
MOV.B:S
Apr 14, 2006
Instruction at Address Indicated by RMADi Register
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8
#IMM,dest (However, dest = A0 or A1)
page 91 of 376
SUB.B:S
MOV.B:S
STZX.B:S
PUSHM
JSRS
#IMM8,dest
#IMM8,dest
#IMM81,#IMM82,dest
src
#IMM8
STZ.B:S
AND.B:S
POPM dest
#IMM8,dest
#IMM8,dest
RMAD0
RMAD1
RMAD2
RMAD3
Address Match Interrupt Register
Value of PC that is Saved to Stack Area
Address indicated by RMADi
register + 2
Address indicated by RMADi
register + 1
10. Interrupts