M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 181

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.14 Serial Data Logic Switching
Figure 15.15 Transfer Clock Output from Multiple Pins
15.1.1.5 Serial Data Logic Switching Function
15.1.1.6 Transfer Clock Output From Multiple Pins (UART1)
When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has
its logic reversed before being transmitted. Similarly, the receive data has its logic reversed when read
from the UiRB register. Figure 15.14 shows the Serial Data Logic Switching.
Use bits CLKMD1 to CLKMD0 in the UCON register to select one of the two transfer clock output pins.
Figure 15.15 shows the Transfer Clock Output from Multiple Pins. This function can be used when the
selected transfer clock for UART1 is an internal clock.
Apr 14, 2006
(1) When the UiLCH bit in the UiC1 register = 0 (no reverse)
(2) When the UiLCH bit = 1 (reverse)
i = 0 to 2
* This applies to the case where the CKPOL bit in the UiC0 register = 0
Transfer clock
Transfer clock
* This applies to the case where the CKDIR bit in the U1MR register
(transmit data output at the falling edge and the receive data taken in
at the rising edge of the transfer clock) and the UFORM bit = 0 (LSB first).
= 0 (internal clock) and the CLKMD1 bit in the UCON register = 1
(transfer clock output from multiple pins).
page 157 of 376
(no reverse)
CLKS1(P6_4)
(reverse)
TXD1(P6_7)
CLK1(P6_5)
MCU
TXDi
TXDi
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
D0
D0
Transfer enabled when
the CLKMD0 bit in the
UCON register = 0
D1
D1
IN
CLK
D2
D2
D3
D3
D4
D4
D5
D5
Transfer enabled when
the CLKMD0 bit = 1
D6
D6
IN
CLK
D7
D7
15. Serial Interface