M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 64

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
7. Bus
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data
input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to CS3,
_____
RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK.
7.1 Bus Mode
Table 7.1 Difference between Separate Bus and Multiplexed Bus
NOTES :
P0_0 to P0_7/D0 to D7
P1_0 to P1_7/D8 to D15
P2_0/A0(/D0/-)
P2_1 to P2_7/A1 to A7
(/D1 to D7/D0 to D6)
P3_0/A8(/-/D7)
The bus mode, either multiplexed or separate, can be selected using bits PM05 to PM04 in the PM0 register.
7.1.1 Separate Bus
7.1.2 Multiplexed Bus
In this bus mode, data and address are separate.
In this bus mode, data and address are multiplexed.
7.1.2.1 When the input level on BYTE pin is high (8-bit data bus)
7.1.2.2 When the input level on BYTE pin is low (16-bit data bus)
Table 7.1 shows the Difference between Separate Bus and Multiplexed Bus.
1. See Table 7.6 Pin Functions for Each Processor Mode for bus control signals other than the above.
2. It changes with a setup of bits PM05 to PM04 in the PM0 register, and area to access. See Table 7.6
________ ______
D0 to D7 and A0 to A7 are multiplexed.
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15.
External devices connecting to a multiplexed bus are allocated to only the even addresses of the
MCU. Odd addresses cannot be accessed.
Pin Functions for Each Processor Mode for details.
Pin Name
Apr 14, 2006
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(1)
page 40 of 376
Separate Bus
________ __________
D8 to D15
D0 to D7
A1 to A7
A0
A8
_________
A1 to A7 D1 to D7
P1_0 to P1_7
A0
BYTE = H
(NOTE 2)
I/O Port
A8
D0
Multiplexed Bus
A1 to A7 D0 to D6
A8
BYTE = L
(NOTE 2)
(NOTE 2)
A0
_______
D7
_______
7. Bus