M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 109

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 10.7 Stack Status Before and After Acceptance of Interrupt Request
Figure 10.8 Register Saving Operation
10.5.7 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 10.7 shows the Stack Status Before and After Acceptance of Interrupt Request.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
The register saving operation carried out in the interrupt sequence is dependent on whether the SP
the time of acceptance of an interrupt request, is even or odd. If the SP
the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time.
Figure 10.8 shows the Register Saving Operation.
NOTE:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
(1)SP contains even number
PCL : 8 low-order bits of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH: 4 high-order bits of FLG
NOTE:
Apr 14, 2006
[SP] - 5 (Odd)
[SP] - 4 (Even)
[SP] - 3 (Odd)
[SP] - 2 (Even)
[SP] - 1 (Odd)
[SP]
by the U flag. Otherwise, it is the ISP.
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Address
Stack status before interrupt request is acknowledged
PCL : 8 low-order bits of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH: 4 high-order bits of FLG
(Even)
Address
m - 4
m - 3
m - 2
m - 1
m
m + 1
MSB
FLGH
Content of previous stack
Content of previous stack
page 85 of 376
Stack
FLGL
PCM
PCL
Stack
PCH
LSB
Sequence in which order
registers are saved
Finished saving registers
in two operations.
(2) Saved simultaneously,
(1) Saved simultaneously,
[SP]
SP value before
interrupt request
is accepted.
all 16 bits
all 16 bits
(2)SP contains odd number
[SP] - 5 (Even)
[SP] - 4 (Odd)
[SP] - 3 (Even)
[SP] - 2 (Odd)
[SP] - 1 (Even)
[SP]
Stack status after interrupt request is acknowledged
Address
(Odd)
Address
m - 4
m - 3
m - 2
m - 1
m
m + 1
MSB
Content of previous stack
Content of previous stack
FLGH
FLGH
Stack
FLGL
PCM
Stack
PCL
PCM
FLGL
PCL
(1)
PCH
is even, the FLG register and
PCH
LSB
Finished saving registers
in four operations.
Sequence in which order
registers are saved
[SP]
New SP value
(3)
(4)
(1)
(2)
Saved,8 bits
at a time
10. Interrupts
(1)
, at