M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 187

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.18 Receive Operation
Table 15.9 Example of Bit Rates and Settings
i = 0 to 2
NOTE:
Bit Rate
14400
19200
28800
31250
38400
51200
15.1.2.1 Bit Rates
1. 24 MHz is available Normal-ver. only.
(bps)
1200
2400
4800
9600
• Example of receive timing when transfer data is 8-bit long (parity disabled, one stop bit)
RE bit in
UiC1 register
The above timing diagram applies to the case where the register bits are set as follows:
RXDi
Transfer clock
IR bit in
SiRIC register
In UART mode, the frequency set by the UiBRG register (i = 0 to 2) divided by 16 become the bit rates.
Table 15.9 lists an Example of Bit Rates and Settings.
UiBRG count
source
RTSi
RI bit in
UiC1 register
i = 0 to 2
Apr 14, 2006
PRYE bit in UiMR register = 0 (parity disabled)
STPS bit in UiMR register = 0 (1 stop bit)
CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
Count Source
of UiBRG
"H"
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
"L"
1
0
1
0
1
0
page 163 of 376
Reception triggered when transfer clock
is generated by falling edge of start bit
Set Value of
Peripheral Function Clock: 16 MHz Peripheral Function Clock: 20 MHz Peripheral Function Clock: 24 MHz
103 (67h)
103 (67h)
UiBRG: n
51 (33h)
25 (19h)
68 (44h)
51 (33h)
34 (22h)
31 (1Fh)
25 (19h)
19 (13h)
Start bit
Sampled "L"
Bit Rate
14493
19231
28571
31250
38462
50000
(bps)
1202
2404
4808
9615
Set to 0 by an interrupt request acknowledgement or by program
D0
Set Value of
129 (81h)
129 (81h)
UiBRG: n
64 (40h)
32 (20h)
86 (56h)
64 (40h)
42 (2Ah)
39 (27h)
32 (20h)
23 (17h)
Receive data taken in
Transferred from UARTi receive
register to UiRB register
D1
Bit Rate
14368
19231
29070
31250
37879
52083
(bps)
1202
2404
4735
9615
D7
Set Value of
155 (9Bh)
155 (9Bh)
103 (67h)
UiBRG: n
77 (4Dh)
38 (26h)
77 (4Dh)
51 (33h)
47 (2Fh)
38 (26h)
28 (1Ch)
Stop bit
15. Serial Interface
Bit Rate
14423
19231
28846
31250
38462
51724
(bps)
1202
2404
4808
9615
(1)