M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 68

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 7.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal
7.2.6 RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on
the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 7.4 shows an Example in which Wait State was Inserted into Read Cycle by RDY
Signal. To use the RDY signal, set the corresponding bit (bits CS3W to CS0W) in the CSR register to 0
(with wait state). When not using the RDY signal, the RDY pin must be pulled-up.
________
Apr 14, 2006
________
In an instance of multiplexed bus
In an instance of separate bus
tsu(RDY-BCLK): RDY input setup time
Shown above is the case where bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register are
00b (one wait state).
RD
RDY
RD
RDY
BCLK
CSi
(i=0 to 3)
BCLK
CSi
(i=0 to 3)
page 44 of 376
: Wait using RDY signal
: Wait using software
________
_______
________
_______
Accept timing of RDY signal
_____
________
________
tsu(RDY - BCLK)
________
Accept timing of RDY signal
______
________
tsu(RDY - BCLK)
________
__________
________
________
________
7. Bus