M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 125

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 12.5 Transfer Cycles for Source Read
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
(3) When the source read cycle under condition (1) has one wait state inserted
(4) When the source read cycle under condition (2) has one wait state inserted
NOTE:
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
1. The same timing changes occur with the respective conditions at the destination as at the source.
transfer unit is 16 bits and an 8-bit bus is used
Apr 14, 2006
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
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CPU use
CPU use
Source
Source
Source
Source
Source
Source
Source + 1
Source
Source
Destination
Source + 1
Destination
Destination
Destination
Source + 1
Destination
Destination
Source + 1
Dummy
cycle
Dummy
cycle
Dummy
Dummy
cycle
cycle
Destination
Dummy
cycle
Dummy
cycle
Destination
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
Dummy
cycle
Dummy
cycle
CPU use
CPU use
12. DMAC