M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 194

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 15.12 I
i = 0 to 2
NOTES:
Source of interrupt
number 6, 7, and
10
Source of interrupt
number 15, 17, and
19
Source of interrupt
number 16, 18, and
20
Timing for transferring
data from UART
reception shift register
to UiRB register
UARTi transmission
output delay
Functions of pins
P6_3, P6_7, and P7_0
Functions of pins
P6_2, P6_6, and P7_1
Functions of pins
P6_1, P6_5, and P7_2
Noise filter width
Read RXDi and
SCLi pins levels
Initial value of TXDi
and SDAi outputs
Initial and end
value of SCLi
DMA1 source
Store received
data
Read received
data
1. If the interrupt source is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to
2. Set the initial value of SDAi output while bits SMD2 to SMD0 in the UiMR register = 000b (serial interface disabled).
3. Second data transfer to the UiRB register (rising edge of SCLi 9th bit)
4. First data transfer to the UiRB register (falling edge of SCLi 9th bit)
5. See Figure 15.26 STSPSEL Bit Functions.
6. See Figure 15.24 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR06 bit in the IFSR0 register to 1 (interrupt source: UART0 bus collision detection).
(1) (5) (7)
(1) (6)
(1) (6)
Function
1 (interrupt requested). (Refer to 23.6 Interrupts.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to set
the IR bit to 0 (interrupt not requested) after changing those bits.
• Bits SMD2 to SMD0 in UiMR register
• IICM2 bit in UiSMR2 register
When using UART1, be sure to set the IFSR07 bit in the IFSR0 register to 1 (interrupt source: UART1 bus collision detection).
Apr 14, 2006
(6)
2
C Mode Functions
(SMD2 to SMD0 =
or completed
output selected
corresponding port
direction bit = 0
1st to 8th bits of the received data are stored into bits
7 to 0 in the UiRB register
-
UARTi transmission
Transmission started
(selected by UiIRS)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TXDi output
RXDi input
CLKi input or
15 ns
Possible when the
CKPOL = 0 (H)
CKPOL = 1 (L)
-
UARTi reception
The UiRB register status is read
Serial I/O Mode
001b, IICM = 0)
page 170 of 376
Synchronous
Clock
Start condition detection or stop condition detection
(See Table 15.13 STSPSEL Bit Functions)
No acknowledgment detection
(NACK)
Rising edge of SCLi 9th bit
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
Rising edge of SCLi 9th bit
Delayed
SDAi input/output
SCLi input/output
- (Cannot be used in I
200 ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I
H
Acknowledgment detection (ACK)
(No clock delay)
CKPH = 0
• IICM bit in UiSMR register
• CKPH bit in UiSMR3 register
(NACK/ACK interrupt)
IICM2 = 0
I
2
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
L
(Clock delay)
CKPH = 1
2
C mode)
UARTi transmission
Rising edge of
SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Falling edge of
SCLi 9th bit
H
UARTi reception
Falling edge of SCLi 9th bit
1st to 7th bits of the received data are stored into
bits 6 to 0 in the UiRB
register, 8th bit is stored into
bit 8 in the UiRB register
(No clock delay)
(UART transmit/receive interrupt)
CKPH = 0
2
C mode
IICM2 = 1
UARTi transmission
Falling edge of
SCLi next to the
9th bit
Falling and rising
edges of SCLi 9th
bit
L
1st to 8th bits are
stored into bit 7 to bit
0 in UiRB register
Bit 6 to bit 0 in the UiRB
register
7 to bit 1. Bit 8 in the UiRB
register is read as bit 0.
15. Serial Interface
(Clock delay)
(2)
CKPH = 1
(4)
are read as bit
(3)