M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 183

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 15.5 UART Mode Specifications
i = 0 to 2
NOTES:
Transfer data format
Transfer clock
Transmit/receive control
Transmit start condition
Receive start condition
Interrupt request
generation timing
Error detection
Select function
15.1.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data
format. Table 15.5 lists the UART Mode Specifications. Table 15.6 lists the Registers to be Used and
Setting in UART Mode.
1. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register.
2. If an overrun error occurs, the receive data of UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the
UARTi receive register to the UiRB register.
Apr 14, 2006
Item
page 159 of 376
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• CKDIR bit in UiMR register = 0 (internal clock) : fj/(16(n+1))
• The CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
Selectable from CTS function, RTS function or CTS/RTS function disabled
Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
•
Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection
For transmission, one of the following conditions can be selected
• The UiIRS bit
• The UiIRS bit =1 (transmission completed): when the serial interface finished
For reception
• When transferring data from the UARTi receive register to the UiRB register
• Overrun error
• Framing error
• Parity error
• Error sum flag
• LSB first, MSB first selection
• Serial data logic switch
• TXD, RXD I/O polarity switch
•
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
fEXT: Input from CLKi pin.
If CTS function is selected, input on the CTSi pin = L
to the UARTi transmit register (at start of transmission)
transmitting data from the UARTi transmit register
(at completion of reception)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the bit one before the last stop bit of the next data
This error occurs when the number of stop bits set is not detected
This error occurs when if parity is enabled, the number of 1’s in parity and character
bits does not match the number of 1’s set
This flag is set to 1 when any of the overrun, framing, or parity errors occur
Whether to start transmitting or receiving data begins with bit 0 or begins with bit 7 can
be selected
This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed.
This function reverses the polarities of the TXD pin output and RXD pin input.
The logic levels of all I/O data is reversed.
Separate CTS/RTS pins (UART0)
_________
CTS0 and RTS0 are input/output from separate pins
_______
_______ _______
_________
(3)
(1)
(2)
(3)
_______
= 0 (transmit buffer empty): when transferring data from the UiTB register
n :Setting value of the UiBRG register
_______
Specification
________
_______ _______
15. Serial Interface
00h to FFh