M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 56

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
NOTE:
Figure 5.2 Reset Sequence
Table 5.1 Pin Status when RESET Pin Level is “L”
P0
P1
P2, P3, P4_0 to P4_3 Input port
P4_4
P4_5 to P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
P6, P7, P8_0 to P8_4, Input port
P8_6, P8_7, P9, P10
1. Shown here is the valid pin state when the internal power supply voltage has stabilized after power-on.
When CNVSS = VCC, the pin state is undefined until the internal power supply voltage stabilizes.
Pin Name
Apr 14, 2006
Microprocessor
mode BYTE = H
Microprocessor
mode BYTE = L
VCC
RD
Address
CS0
XIN
RESET
BCLK
Address
WR
CS0
RD
WR
Addres
Single-chip
mode
s
td(P-R)
page 32 of 376
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
More than
20 cycles
are needed
CNVSS = VSS
____________
BCLK
28cycles
Data input
Data input
Address output (undefined)
______
CS0 output (“H” is output)
Input port (Pulled high)
______
WR output (“H” is output)
________
BHE output (undefined)
______
RD output (“H” is output)
BCLK output
___________
HLDA output
(The output value depends on (The output value depends on
the input to the HOLD pin)
__________
HOLD input
ALE output (“L” is output)
________
RDY input
Input port
FFFFCh
FFFFCh
FFFFCh
BYTE = VSS
FFFFEh
Status
Content of reset vector
FFFFDh
__________
FFFFEh
CNVSS = VCC
Content of reset vector
FFFFEh
Data input
Input port
Address output (undefined)
______
CS0 output (“H” is output)
Input port (Pulled high)
______
WR output (“H” is output)
________
BHE output (undefined)
______
RD output (“H” is output)
BCLK output
___________
HLDA output
__________
HOLD input
ALE output (“L” is output)
________
RDY input
Input port
the input to the HOLD pin)
Content of reset vector
(1)
BYTE = VCC
__________
5. Resets