LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 104

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
6. MAM configuration
UM10237_4
User manual
Table 96.
[1]
[2]
Table 97.
[1]
After reset the MAM defaults to the disabled state. Software can turn memory access
acceleration on or off at any time. This allows most of an application to be run at the
highest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.
Program Memory Request Type
Sequential access, data in latches
Sequential access, data not in latches
Non-sequential access, data in latches
Non-sequential access, data not in
latches
Data Memory Request Type
Sequential access, data in latches
Sequential access, data not in latches
Non-sequential access, data in latches
Non-sequential access, data not in latches Initiate Fetch
Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the
holding latches if the data is present. Instruction prefetch is enabled. Non-sequential
instruction accesses initiate Flash read operations (see
that all branches cause memory fetches. All data operations cause a Flash read
because buffered data access timing is hard to predict and is very situation dependent.
Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is
contained in one of the corresponding holding latches is fulfilled from the latch.
Instruction prefetch is enabled. Flash read operations are initiated for instruction
prefetch and code or data values not available in the corresponding holding latches.
Instruction prefetch is enabled in modes 1 and 2.
The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
MAM responses to program accesses of various types
MAM responses to data and DMA accesses of various types
Rev. 04 — 26 August 2009
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
MAM Mode
0
Initiate Fetch
Initiate Fetch
Initiate Fetch
Initiate Fetch
MAM Mode
0
Initiate Fetch
Initiate Fetch
Initiate Fetch
[2]
[2]
[1]
[1]
1
Use Latched
Data
Initiate Fetch
Initiate Fetch
Initiate Fetch
Initiate Fetch
1
Initiate Fetch
Initiate Fetch
Initiate Fetch
Table note
[1]
[1]
[1][2]
[1]
[1]
[1]
6–2). This means
UM10237
© NXP B.V. 2009. All rights reserved.
2
Use Latched
Data
Initiate Fetch
Use Latched
Data
Initiate Fetch
2
Use Latched
Data
Initiate Fetch
Use Latched
Data
Initiate Fetch
[1]
[1]
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[1]
[1]