LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 682
![IC ARM7 MCU ROMLESS 208TFBGA](/photos/12/32/123248/mfg_lpc24xx_sml.jpg)
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
8. Code Read Protection (CRP)
UM10237_4
User manual
Code Read Protection is a mechanism that allows user to enable different levels of
security in the system so that access to the on-chip Flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in Flash
location at 0x000001FC. IAP commands are not affected by the code read protection.
Starting with bootloader version 3.2 three levels of CRP are implemented. Earlier
bootloader versions had only CRP2 option implemented.
Important: any CRP change becomes effective only after the device has gone
through a power cycle.
Table 601. Code Read Protection options
Name Pattern
CRP1 0x12345678
CRP2 0x87654321
CRP3 0x43218765
programmed
in 0x000001FC
Rev. 04 — 26 August 2009
Description
Access to chip via the JTAG pins is disabled. This mode allows partial
Flash update using the following ISP commands and restrictions:
This mode is useful when CRP is required and Flash field updates are
needed but all sectors can not be erased. Since compare command is
disabled in case of partial updates the secondary loader should
implement checksum mechanism to verify the integrity of the Flash.
Access to chip via the JTAG pins is disabled. The following ISP
commands are disabled:
When CRP2 is enabled the ISP erase command only allows erasure of
all user sectors.
Access to chip via the JTAG pins is disabled. ISP entry by pulling P2.10
LOW is disabled if a valid user code is present in Flash sector 0.
This mode effectively disables ISP overide using P2.10 pin. It is up to the
user’s application to provide need Flash update mechanism using IAP
calls or call reinvoke ISP command to enable Flash update via UART0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
•
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Chapter 30: LPC24XX Flash memory programming firmware
Write to RAM command can not access RAM below 0x40000200
Copy RAM to Flash command can not write to Sector 0
Erase command can erase Sector 0 only when all sectors are
selected for erase
Compare command is disabled
Read command is disabled
Read Memory command
Write to RAM command
Go command
Copy RAM to Flash command
Compare command
UM10237
© NXP B.V. 2009. All rights reserved.
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