LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 613
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
5. Register description
UM10237_4
User manual
Fig 127. Simple I
TRANSMITTER
(MASTER)
2
S configurations and bus timing
SCK
WS
SD
SCK: serial clock
WS: word select
SD: serial data
Table 23–531
their functions. Following the table are details for each register.
Table 531. Summary of I
Name
I2SDAO
I2SDAI
I2STXFIFO
I2SRXFIFO
I2SSTATE
I2SDMA1
I2SDMA2
right channel
word n-1
TRANSMITTER
Description
Digital Audio Output Register. Contains control
bits for the I
Digital Audio Input Register. Contains control
bits for the I
Transmit FIFO. Access register for the 8
transmitter FIFO.
Receive FIFO. Access register for the 8
receiver FIFO.
Status Feedback Register. Contains status
information about the I
DMA Configuration Register 1. Contains control
information for DMA request 1.
DMA Configuration Register 2. Contains control
information for DMA request 2.
shows the registers associated with the I
RECEIVER
(SLAVE)
(SLAVE)
MSB
Rev. 04 — 26 August 2009
2
2
2
S registers
S transmit channel.
S receive channel.
CONTROLLER
(MASTER)
SCK
WS
SD
2
S interface.
left channel
word n
RECEIVER
TRANSMITTER
(SLAVE)
(SLAVE)
×
×
32 bit
32 bit
Chapter 23: LPC24XX I
LSB
2
S interface and a summary of
SCK: serial clock
WS: word select
SD: serial data
Access Reset
R/W
R/W
WO
RO
RO
R/W
R/W
MSB
right channel
word n+1
Value
UM10237
© NXP B.V. 2009. All rights reserved.
RECEIVER
[1]
(MASTER)
Address
0xE008 8000
0xE008 8004
0xE008 8008
0xE008 800C
0xE008 8010
0xE008 8014
0xE008 8018
2
S interface
613 of 792
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