LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 113
![IC ARM7 MCU ROMLESS 208TFBGA](/photos/12/32/123248/mfg_lpc24xx_sml.jpg)
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
3.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010)
3.5 Interrupt Enable Clear Register (VICIntEnClear - 0xFFFF F014)
3.6 Interrupt Select Register (VICIntSelect - 0xFFFF F00C)
Table 105. Raw Interrupt Status register (VICRawIntr - address 0xFFFF F008) bit description
This is a read/write accessible register. This register controls which of the 32 combined
hardware and software interrupt requests are enabled to contribute to FIQ or IRQ.
Table 106. Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit description
This is a write only register. This register allows software to clear one or more bits in the
Interrupt Enable register (see
0xFFFF F010)” on page
Table 107. Interrupt Enable Clear register (VICIntEnClear - address 0xFFFF F014) bit
This is a read/write accessible register. This register classifies each of the 32 interrupt
requests as contributing to FIQ or IRQ.
Bit
31:0 See
Bit
31:0 See
Bit
31:0 See
Symbol
7–117
“Interrupt
sources bit
allocation
table”.
Symbol
7–117
“Interrupt
sources bit
allocation
table”.
Symbol
7–117
“Interrupt
sources bit
allocation
table”.
Table
Table
Table
description
Description
When this register is read, 1s indicate interrupt requests or software
interrupts that are enabled to contribute to FIQ or IRQ.
When this register is written, ones enable interrupt requests or
software interrupts to contribute to FIQ or IRQ, zeroes have no
effect. See
(VICIntEnClear - 0xFFFF F014)” on page 113
below for how to disable interrupts.
Value Description
0
1
Value Description
0
1
Rev. 04 — 20 August 2009
113), without having to first read it.
Neither the hardware nor software interrupt request with this
bit number are asserted.
The hardware or software interrupt request with this bit
number is asserted.
Writing a 0 leaves the corresponding bit in VICIntEnable
unchanged.
Writing a 1 clears the corresponding bit in the Interrupt
Enable register, thus disabling interrupts for this request.
Section 7–3.4 “Interrupt Enable Register (VICIntEnable -
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
Section 7–3.5 “Interrupt Enable Clear Register
and
Table 7–107
UM10237
© NXP B.V. 2009. All rights reserved.
113 of 792
Reset
value
-
Reset
value
-
Reset
value
0
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