LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 778
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
1
2
3
3.1
3.2
4
5
6
6.1
6.2
6.3
6.4
6.5
6.6
Chapter 11: LPC24XX Ethernet
1
2
3
4
5
5.1
5.2
5.3
5.4
UM10237_4
User manual
How to read this chapter . . . . . . . . . . . . . . . . 194
Basic configuration . . . . . . . . . . . . . . . . . . . . 194
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 196
Register description . . . . . . . . . . . . . . . . . . . 196
How to read this chapter . . . . . . . . . . . . . . . . 211
Basic configuration . . . . . . . . . . . . . . . . . . . . 211
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Ethernet architecture. . . . . . . . . . . . . . . . . . . 213
Pin Function Select Register 5 (PINSEL5 -
0xE002 C014). . . . . . . . . . . . . . . . . . . . . . . . 184
Pin Function Select Register 6 (PINSEL6 -
0xE002 C018). . . . . . . . . . . . . . . . . . . . . . . . 186
Pin Function Select Register 7 (PINSEL7 -
0xE002 C01C) . . . . . . . . . . . . . . . . . . . . . . . 186
Pin Function Select Register 8 (PINSEL8 -
0xE002 C020). . . . . . . . . . . . . . . . . . . . . . . . 187
Pin Function Select Register 9 (PINSEL9 -
0xE002 C024). . . . . . . . . . . . . . . . . . . . . . . . 188
Pin Function Select Register 10 (PINSEL10 -
0xE002 C028). . . . . . . . . . . . . . . . . . . . . . . . 189
Pin Function Select Register 11 (PINSEL11 -
0xE002 C02C) . . . . . . . . . . . . . . . . . . . . . . . 190
Pin Mode select register 0 (PINMODE0 -
0xE002 C040). . . . . . . . . . . . . . . . . . . . . . . . 190
Pin Mode select register 1 (PINMODE1 -
0xE002 C044). . . . . . . . . . . . . . . . . . . . . . . . 191
Digital I/O ports . . . . . . . . . . . . . . . . . . . . . . . 194
Interrupt generating digital ports . . . . . . . . . . 195
GPIO port Direction register IODIR and
FIODIR(IO[0/1]DIR - 0xE002 80[0/1]8 and
FIO[0/1/2/3/4]DIR - 0x3FFF C0[0/2/4/6/8]0) . 199
GPIO port output Set register IOSET and
FIOSET(IO[0/1]SET - 0xE002 80[0/1]4 and
FIO[0/1/2/3/4]SET - 0x3FFF C0[1/3/5/7/9]8) 200
GPIO port output Clear register IOCLR and
FIOCLR (IO[0/1]CLR - 0xE002 80[0/1]C and
FIO[0/1/2/3/4]CLR - 0x3FFF C0[1/3/5/7/9]C) 202
GPIO port Pin value register IOPIN and FIOPIN
(IO[0/1]PIN - 0xE002 80[0/1]0 and
FIO[0/1/2/3/4]PIN - 0x3FFF C0[1/3/5/7/9]4) . 203
Fast GPIO port Mask register
FIOMASK(FIO[0/1/2/3/4]MASK -
0x3FFF C0[1/3/5/7/9]0) . . . . . . . . . . . . . . . . 205
GPIO interrupt registers . . . . . . . . . . . . . . . . 207
Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Example PHY Devices . . . . . . . . . . . . . . . . . 215
DMA engine functions . . . . . . . . . . . . . . . . . 215
Overview of DMA operation . . . . . . . . . . . . . 216
Rev. 04 — 26 August 2009
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
7
7.1
7.2
7.3
7.4
5.5
6
7
7.1
7.1.1
7.1.2
Chapter 36: LPC24XX Supplementary information
GPIO usage notes . . . . . . . . . . . . . . . . . . . . . 209
Pin description . . . . . . . . . . . . . . . . . . . . . . . 217
Register description . . . . . . . . . . . . . . . . . . . 218
Pin Mode select register 2 (PINMODE2 -
0xE002 C048) . . . . . . . . . . . . . . . . . . . . . . . 191
Pin Mode select register 3 (PINMODE3 -
0xE002 C04C) . . . . . . . . . . . . . . . . . . . . . . . 191
Pin Mode select register 4 (PINMODE4 -
0xE002 C050) . . . . . . . . . . . . . . . . . . . . . . . 191
Pin Mode select register 5 (PINMODE5 -
0xE002 C054) . . . . . . . . . . . . . . . . . . . . . . . 192
Pin Mode select register 6 (PINMODE6 -
0xE002 C058) . . . . . . . . . . . . . . . . . . . . . . . 192
Pin Mode select register 7 (PINMODE7 -
0xE002 C05C) . . . . . . . . . . . . . . . . . . . . . . . 192
Pin Mode select register 8 (PINMODE8 -
0xE002 C060) . . . . . . . . . . . . . . . . . . . . . . . 192
Pin Mode select register 9 (PINMODE9 -
0xE002 C064) . . . . . . . . . . . . . . . . . . . . . . . 193
GPIO overall Interrupt Status register (IOIntStatus
- 0xE002 8080) . . . . . . . . . . . . . . . . . . . . . . 207
GPIO Interrupt Enable for Rising edge register
(IO0IntEnR - 0xE002 8090 and IO2IntEnR -
0xE002 80B0) . . . . . . . . . . . . . . . . . . . . . . . 207
GPIO Interrupt Enable for Falling edge register
(IO0IntEnF - 0xE002 8094 and IO2IntEnF -
0xE002 80B4) . . . . . . . . . . . . . . . . . . . . . . . 207
GPIO Interrupt Status for Rising edge register
(IO0IntStatR - 0xE002 8084 and IO2IntStatR -
0xE002 80A4) . . . . . . . . . . . . . . . . . . . . . . . 208
GPIO Interrupt Status for Falling edge register
(IO0IntStatF - 0xE002 8088 and IO2IntStatF -
0xE002 80A8) . . . . . . . . . . . . . . . . . . . . . . . 208
GPIO Interrupt Clear register (IO0IntClr -
0xE002 808C and IO2IntClr - 0xE002 80AC) 208
Example 1: sequential accesses to IOSET and
IOCLR affecting the same GPIO pin/bit . . . . 209
Example 2: an instantaneous output of 0s and 1s
on a GPIO port. . . . . . . . . . . . . . . . . . . . . . . 209
Writing to IOSET/IOCLR vs. IOPIN . . . . . . . 210
Output signal frequency considerations when
using the legacy and enhanced GPIO
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Ethernet Packet . . . . . . . . . . . . . . . . . . . . . . 216
Ethernet MAC register definitions . . . . . . . . 220
MAC Configuration Register 1 (MAC1 -
0xFFE0 0000) . . . . . . . . . . . . . . . . . . . . . . . 221
MAC Configuration Register 2 (MAC2 -
0xFFE0 0004) . . . . . . . . . . . . . . . . . . . . . . . 221
UM10237
© NXP B.V. 2009. All rights reserved.
778 of 792
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