LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 132

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
Table 120. Pin description
UM10237_4
User manual
Symbol
P2[12]/EINT2/
MCIDAT2/
I2STX_WS
P2[13]/EINT3/
MCIDAT3/
I2STX_SDA
P2[16]/CAS
P2[17]/RAS
P2[18]/
CLKOUT0
P2[19]/
CLKOUT1
P2[20]/DYCS0
P2[21]/DYCS1
P2[24]/
CKEOUT0
P2[25]/
CKEOUT1
P2[28]/
DQMOUT0
P2[29]/
DQMOUT1
P3[0] to P3[31]
P3[0]/D0
P3[1]/D1
P3[2]/D2
P3[3]/D3
Ball
N14
M11
P9
P11
P3
N5
P6
N8
P1
P2
M2
L1
D6
E6
A2
G5
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[6]
[6]
…continued
Type
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
P2[12] — General purpose digital input/output pin.
EINT2 — External interrupt 2 input.
MCIDAT2 — Data line 2 for SD/MMC interface.
I2STX_WS — Transmit Word Select. It is driven by the master and received by
the slave. Corresponds to the signal WS in the I
P2[13] — General purpose digital input/output pin.
EINT3 — External interrupt 3 input.
MCIDAT3 — Data line 3 for SD/MMC interface.
I2STX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I
P2[16] — General purpose digital input/output pin.
CAS — LOW active SDRAM Column Address Strobe.
P2[17] — General purpose digital input/output pin.
RAS — LOW active SDRAM Row Address Strobe.
P2[18] — General purpose digital input/output pin.
CLKOUT0 — SDRAM clock 0.
P2[19] — General purpose digital input/output pin.
CLKOUT1 — SDRAM clock 1.
P2[20] — General purpose digital input/output pin.
DYCS0 — SDRAM chip select 0.
P2[21] — General purpose digital input/output pin.
DYCS1 — SDRAM chip select 1.
P2[24] — General purpose digital input/output pin.
CKEOUT0 — SDRAM clock enable 0.
P2[25] — General purpose digital input/output pin.
CKEOUT1 — SDRAM clock enable 1.
P2[28] — General purpose digital input/output pin.
DQMOUT0 — Data mask 0 used with SDRAM and static devices.
P2[29] — General purpose digital input/output pin.
DQMOUT1 — Data mask 1 used with SDRAM and static devices.
Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 3 pins depends upon the pin function selected via the Pin
Connect block.
Pins P3[16:22] and P3[27:31] are not available.
P3[0] — General purpose digital input/output pin.
D0 — External memory data line 0.
P3[1] — General purpose digital input/output pin.
D1 — External memory data line 1.
P3[2] — General purpose digital input/output pin.
D2 — External memory data line 2.
P3[3] — General purpose digital input/output pin.
D3 — External memory data line 3.
Rev. 04 — 26 August 2009
Chapter 8: LPC24XX Pin configuration
2
S-bus specification.
2
S-bus specification.
UM10237
© NXP B.V. 2009. All rights reserved.
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