LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 313

IC ARM7 MCU ROMLESS 208TFBGA

LPC2460FET208,551

Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2460FET208,551

Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
UM10237_4
User manual
7.9 Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)
The LCD_INTMSK register controls whether various LCD interrupts occur.Setting bits in
this register enables the corresponding raw interrupt LCD_INTRAW status bit values to be
passed to the LCD_INTSTAT register for processing as interrupts.
The contents of the LCD_INTMSK register are described in
Table 268. Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
Bits
4
3:1
0
Bits
31:5
4
3
Function
LcdBW
LcdBpp
LcdEn
Function
reserved
BERIM
VCompIM
Rev. 04 — 26 August 2009
Description
STN LCD monochrome/color selection.
0 = STN LCD is color.
1 = STN LCD is monochrome.
This bit has no meaning in TFT mode.
LCD bits per pixel:
Selects the number of bits per LCD pixel:
000 = 1 bpp.
001 = 2 bpp.
010 = 4 bpp.
011 = 8 bpp.
100 = 16 bpp.
101 = 24 bpp (TFT panel only).
110 = 16 bpp, 5:6:5 mode.
111 = 12 bpp, 4:4:4 mode.
LCD enable control bit.
0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are low.
1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are high.
See LCD power-up and power-down sequence for details on
LCD power sequencing.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
AHB master error interrupt enable.
0: The AHB Master error interrupt is disabled.
1: Interrupt will be generated when an AHB Master error occurs.
Vertical compare interrupt enable.
0: The vertical compare time interrupt is disabled.
1: Interrupt will be generated when the vertical compare time (as
defined by LcdVComp field in the LCD_CTRL register) is
reached.
Chapter 12: LPC24XX LCD controller
Table
12–268.
UM10237
© NXP B.V. 2009. All rights reserved.
313 of 792
Reset
value
0x0
0x0
0x0
Reset
value
-
0x0
0x0

Related parts for LPC2460FET208,551