LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 547
![IC ARM7 MCU ROMLESS 208TFBGA](/photos/12/32/123248/mfg_lpc24xx_sml.jpg)
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.3 SSPn Data Register (SSP0DR - 0xE006 8008, SSP1DR - 0xE003 0008)
Table 472: SSPn Control Register 1 (SSP0CR1 - address 0xE006 8004, SSP1CR1 -
Software can write data to be transmitted to this register, and read data that has been
received.
Table 473: SSPn Data Register (SSP0DR - address 0xE006 8008, SSP1DR - 0xE003 0008) bit
Bit
0
1
2
3
7:4
Bit
15:0
Symbol
LBM
SSE
MS
SOD
-
Symbol
DATA
0xE003 0004) bit description
description
Description
Write: software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1,
indicating that the Tx FIFO is not full. If the Tx FIFO was
previously empty and the SSP controller is not busy on the bus,
transmission of the data will begin immediately. Otherwise the
data written to this register will be sent as soon as all previous
data has been sent (and received). If the data length is less than
16 bits, software must right-justify the data written to this register.
Read: software can read data from this register whenever the
RNE bit in the Status register is 1, indicating that the Rx FIFO is
not empty. When software reads this register, the SSP controller
returns data from the least recent frame in the Rx FIFO. If the
data length is less than 16 bits, the data is right-justified in this
field with higher order bits filled with 0s.
Value
0
1
0
1
0
1
Rev. 04 — 26 August 2009
Description
Loop Back Mode.
During normal operation.
Serial input is taken from the serial output (MOSI or MISO)
rather than the serial input pin (MISO or MOSI
respectively).
SSP Enable.
The SSP controller is disabled.
The SSP controller will interact with other devices on the
serial bus. Software should write the appropriate control
information to the other SSP registers and interrupt
controller registers, before setting this bit.
Master/Slave Mode.This bit can only be written when the
SSE bit is 0.
The SSP controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
The SSP controller acts as a slave on the bus, driving
MISO line and receiving SCLK, MOSI, and SSEL lines.
Slave Output Disable. This bit is relevant only in slave
mode (MS = 1). If it is 1, this blocks this SSP controller
from driving the transmit data line (MISO).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 20: LPC24XX SSP interface SSP0/1
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0x0000
0
NA
Reset
Value
0
0
0
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