LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 310

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
UM10237_4
User manual
7.6 Upper Panel Frame Base Address register (LCD_UPBASE, RW -
7.7 Lower Panel Frame Base Address register (LCD_LPBASE, RW -
Table 264. Line End Control register (LCD_LE, RW - 0xFFE1 000C)
0xFFE1 0010)
The LCD_UPBASE register is the color LCD upper panel DMA base address register, and
is used to program the base address of the frame buffer for the upper panel. LCDUPBase
(and LCDLPBase for dual panels) must be initialized before enabling the LCD controller.
The base address must be doubleword aligned.
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
The contents of the LCD_UPBASE register are described in
Table 265. Upper Panel Frame Base register (LCD_UPBASE, RW - 0xFFE1 0010)
0xFFE1 0014)
The LCD_LPBASE register is the color LCD lower panel DMA base address register, and
is used to program the base address of the frame buffer for the lower panel. LCDLPBase
must be initialized before enabling the LCD controller. The base address must be
doubleword aligned.
Bits
31:17
16
15:7
6:0
Bits
31:3
2:0
Function
reserved
LEE
reserved
LED
Function
LCDUPBASE
reserved
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
LCD Line end enable.
0 = LCDLE disabled (held LOW).
1 = LCDLE signal active.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Line-end delay.
Controls Line-end signal delay from the rising-edge of the last
panel clock, LCDDCLK. Program with number of LCDCLK clock
periods minus 1.
Description
LCD upper panel base address.
This is the start address of the upper panel frame data in
memory and is doubleword aligned.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 12: LPC24XX LCD controller
Table
12–265.
UM10237
© NXP B.V. 2009. All rights reserved.
310 of 792
Reset
value
-
0x0
-
0x0
Reset
value
0x0
-