LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 673

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
6. Operation
UM10237_4
User manual
6.1 Hardware-triggered conversion
6.2 Interrupts
6.3 Accuracy vs. digital receiver
If the BURST bit in the ADCR is 0 and the START field contains 010-111, the A/D
converter will start a conversion when a transition occurs on a selected pin or Timer Match
signal. The choices include conversion on a specified edge of any of 4 Match signals, or
conversion on a specified edge of either of 2 Capture/Match pins. The pin state from the
selected pad or the selected Match signal, XORed with ADCR bit 27, is used in the edge
detection logic.
An interrupt is requested to the Vectored Interrupt Controller (VIC) when the ADINT bit in
the ADSTAT register is 1. The ADINT bit is one when any of the DONE bits of A/D
channels that are enabled for interrupts (via the ADINTEN register) are one. Software
can use the Interrupt Enable bit in the VIC that corresponds to the ADC to control whether
this results in an interrupt. The result register for an A/D channel that is generating an
interrupt must be read in order to clear the corresponding DONE flag.
While the A/D converter can be used to measure the voltage on any AD0 pin, regardless
of the pin’s setting in the Pin Select register
registers” on page
disabling the pin’s digital receiver.
178), selecting the AD0 function improves the conversion accuracy by
Rev. 04 — 26 August 2009
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
(Table 9–129 “Summary of pin connect block
UM10237
© NXP B.V. 2009. All rights reserved.
673 of 792