LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 295
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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UM10237_4
User manual
6.5.2 Cursor sizes
6.5.3 Cursor movement
6.5.4 Cursor XY positioning
When the display point is inside the bounds of the cursor image, the cursor replaces
frame buffer pixels with cursor pixels.
When the last cursor pixel is displayed, an interrupt is generated that software can use as
an indication that it is safe to modify the cursor image. This enables software controlled
animations to be performed without flickering for frame synchronized cursors.
Two cursor sizes are supported, as shown in
Table 253. Palette data storage for STN monochrome mode.
The following descriptions assume that both the screen and cursor origins are at the top
left of the visible screen (the first visible pixel scanned each frame).
how each pixel coordinate is assumed to be the top left corner of the pixel.
The CRSR_XY register controls the cursor position on the cursor overlay (see Cursor XY
Position register). This provides separate fields for X and Y ordinates.
The CRSR_CFG register (see Cursor Configuration register) provides a FrameSync bit
controlling the visible behavior of the cursor.
X Pixels
32
64
Fig 37. Cursor movement
Y Pixels
32
64
(0,0)
Rev. 04 — 26 August 2009
CRSR_XY(X)
Bits per pixel
2
2
Words per line
2
4
Table
Chapter 12: LPC24XX LCD controller
12–253.
Words in cursor image
64
256
Figure 12–37
UM10237
© NXP B.V. 2009. All rights reserved.
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