LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 504
![IC ARM7 MCU ROMLESS 208TFBGA](/photos/12/32/123248/mfg_lpc24xx_sml.jpg)
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
15.7 End of AF Tables Register (ENDofTable - 0xE003 C014)
15.8 Status registers
15.9 LUT Error Address Register (LUTerrAd - 0xE003 C018)
Table 448. End of AF Tables Register (ENDofTable - address 0xE003 C014) bit description
[1]
The look-up table error status registers, the error addresses, and the flag register provide
information if a programming error in the look-up table RAM during the ID screening was
encountered. The look-up table error address and flag register have only read access. If
an error is detected, the LUTerror flag is set, and the LUTerrorAddr register provides the
information under which address during an ID screening an error in the look-up table was
encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table
interrupt.
Table 449. LUT Error Address Register (LUTerrAd - address 0xE003 C018) bit description
Bit
1:0
11:2
31:12 -
Bit
1:0
10:2
31:11 -
Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
Symbol
-
EndofTable
[1]
Symbol
-
LUTerrAd It the LUT Error bit (below) is 1, this read-only field contains the address
Description
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
in AF Lookup Table RAM, at which the Acceptance Filter encountered
an error in the content of the tables.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
The address above the last active address in the last active AF table.
For compatibility with possible future devices, please write zeroes in
bits 31:12 and 1:0 of this register.
If the eFCAN bit in the AFMR is 0, the largest value that should be
written to this register is 0x800, which allows the last word (address
0x7FC) in AF Lookup Table RAM to be used.
If the eFCAN bit in the AFMR is 1, this value marks the start of the
area of Acceptance Filter RAM, into which the Acceptance Filter will
automatically receive messages for selected IDs on selected CAN
buses. In this case, the maximum value that should be written to this
register is 0x800 minus 6 times the value in SFF_sa. This allows 12
bytes of message storage between this address and the end of
Acceptance Filter RAM, for each Standard ID that is specified
between the start of Acceptance Filter RAM, and the next active AF
table.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
504 of 792
Reset
Value
NA
0
NA
Reset
Value
NA
0
NA
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