LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 452
![IC ARM7 MCU ROMLESS 208TFBGA](/photos/12/32/123248/mfg_lpc24xx_sml.jpg)
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
4.6 UART1 FIFO Control Register (U1FCR - 0xE001 0008, Write Only)
4.7 UART1 Line Control Register (U1LCR - 0xE001 000C)
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.
The U1FCR controls the operation of the UART1 RX and TX FIFOs.
Table 404. UART1 FIFO Control Register (U1FCR - address 0xE001 0008, Write Only) bit
The U1LCR determines the format of the data character that is to be transmitted or
received.
Table 405. UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description
Bit
0
1
2
5:3
7:6
Bit
1:0
2
3
Symbol Value Description
Word
Length
Select
Stop Bit
Select
Parity
Enable
Symbol
FIFO
Enable
RX FIFO
Reset
TX FIFO
Reset
-
RX
Trigger
Level
description
00
01
10
11
0
1
0
1
Value Description
0
1
0
1
0
1
00
01
10
11
5 bit character length.
6 bit character length.
7 bit character length.
8 bit character length.
1 stop bit.
2 stop bits (1.5 if U1LCR[1:0]=00).
Disable parity generation and checking.
Enable parity generation and checking.
Rev. 04 — 26 August 2009
UART1 FIFOs are disabled. Must not be used in the application.
Active high enable for both UART1 Rx and TX FIFOs and
U1FCR[7:1] access. This bit must be set for proper UART1
operation. Any transition on this bit will automatically clear the
UART1 FIFOs.
No impact on either of UART1 FIFOs.
Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx
FIFO and reset the pointer logic. This bit is self-clearing.
No impact on either of UART1 FIFOs.
Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX
FIFO and reset the pointer logic. This bit is self-clearing.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
These two bits determine how many receiver UART1 FIFO
characters must be written before an interrupt is activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Chapter 17: LPC24XX UART1
UM10237
© NXP B.V. 2009. All rights reserved.
452 of 792
Reset
Value
0
0
0
NA
0
Reset
Value
0
0
0
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