LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 432

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
UM10237_4
User manual
4.8 UARTn Line Status Register (U0LSR - 0xE000 C014, U2LSR -
Table 386. UARTn Line Control Register (U0LCR - address 0xE000 C00C,
0xE007 8014, U3LSR - 0xE007 C014, Read Only)
The UnLSR is a read-only register that provides status information on the UARTn TX and
RX blocks.
Table 387. UARTn Line Status Register (U0LSR - address 0xE000 C014,
Bit Symbol
1:0 Word Length
2
3
5:4 Parity Select
6
7
Bit Symbol
0
1
Receiver
Data Ready
(RDR)
Overrun Error
(OE)
Select
Stop Bit Select
Parity Enable
Break Control
Divisor Latch
Access Bit
(DLAB)
U2LCR - 0xE007 800C, U3LCR - 0xE007 C00C) bit description
U2LSR - 0xE007 8014, U3LSR - 0xE007 C014, Read Only) bit description
Value Description
0
1
0
1
Value Description
00
01
10
11
0
1
0
1
00
01
10
11
0
1
0
1
Rev. 04 — 26 August 2009
UnLSR0 is set when the UnRBR holds an unread character
and is cleared when the UARTn RBR FIFO is empty.
UnRBR is empty.
UnRBR contains valid data.
The overrun error condition is set as soon as it occurs. An
UnLSR read clears UnLSR1. UnLSR1 is set when UARTn
RSR has a new character assembled and the UARTn RBR
FIFO is full. In this case, the UARTn RBR FIFO will not be
overwritten and the character in the UARTn RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
5 bit character length
6 bit character length
7 bit character length
8 bit character length
1 stop bit.
2 stop bits (1.5 if UnLCR[1:0]=00).
Disable parity generation and checking.
Enable parity generation and checking.
Odd parity. Number of 1s in the transmitted character and
the attached parity bit will be odd.
Even Parity. Number of 1s in the transmitted character and
the attached parity bit will be even.
Forced "1" stick parity.
Forced "0" stick parity.
Disable break transmission.
Enable break transmission. Output pin UART0 TXD is
forced to logic 0 when UnLCR[6] is active high.
Disable access to Divisor Latches.
Enable access to Divisor Latches.
Chapter 16: LPC24XX UART0/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
0
0
0
0
0
0
Reset
Value
0
0