LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 709

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
UM10237_4
User manual
7.3 Compare <address1> <address2> <no of bytes>
7.4 Reinvoke ISP
7.5 IAP Status Codes
Table 646. IAP Compare command
Table 647. Reinvoke ISP
Table 648. IAP Status Codes Summary
Command
Input
Return Code
Result
Description
Command
Input
Return Code
Result
Description
Status
Code
0
1
2
Mnemonic
CMD_SUCCESS
INVALID_COMMAND
SRC_ADDR_ERROR
Compare
Command code: 56
Param0(DST): Starting RAM address of data bytes to be compared. This address
should be a word boundary.
Param1(SRC): Starting RAM address of data bytes to be compared. This address
should be a word boundary.
Param2: Number of bytes to be compared; should be a multiple of 4.
CMD_SUCCESS |
COMPARE_ERROR |
COUNT_ERROR (Byte count is not a multiple of 4) |
ADDR_ERROR |
ADDR_NOT_MAPPED
Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR.
This command is used to compare the memory contents at two locations.
The result may not be correct when the source or destination includes any
of the first 64 bytes starting from address zero. The first 64 bytes can be
re-mapped to RAM.
Compare
Command code: 57
None
None.
This command is used to invoke the bootloader in ISP mode. It maps boot
vectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, resets
TIMER1 and resets the U0FDR (see
used when a valid user program is present in the external memory and the P2.10
pin is not accessible to force the ISP mode. The command does not disable the
PLL hence it is possible to invoke the bootloader when the part is running off the
PLL. In such case the ISP utility should pass the CCLK (crystal or PLL output
depending on the clock source selection
autobaud handshake.
Another option is to disable the PLL and select the IRC as the clock source before
making this IAP call. In this case frequency sent by ISP is ignored and IRC and
PLL are used to generate CCLK = 14.748 MHz.
Rev. 04 — 26 August 2009
Chapter 31: LPC24XX On-chip bootloader for flashless parts
10
10
Description
Command is executed successfully.
Invalid command.
Source address is not on a word boundary.
Section
Section
16–4.12). This command may be
4–3.1.1) frequency after
UM10237
© NXP B.V. 2009. All rights reserved.
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