LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 105

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
7. Register description
UM10237_4
User manual
7.1 MAM Control Register (MAMCR - 0xE01F C000)
7.2 MAM Timing Register (MAMTIM - 0xE01F C004)
The MAM is controlled by the registers shown in
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
Table 98.
[1]
Two configuration bits select the three MAM operating modes, as shown in
Following any reset, MAM functions are disabled. Software can turn memory access
acceleration on or off at any time allowing most of an application to be run at the highest
possible performance, while certain functions can be run at a somewhat slower but more
predictable rate if more precise timing is required.
Changing the MAM operating mode causes the MAM to invalidate all of the holding
latches, resulting in new reads of Flash information as required. This guarantees
synchronization of the MAM to CPU operation.
Table 99.
The MAM Timing register determines how many CCLK cycles are used to access the
Flash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash
accesses would essentially remove the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.
Name
MAMCR Memory Accelerator Module Control Register.
MAMTIM Memory Accelerator Module Timing control.
Bit
1:0
7:2
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
MAM_mode
_control
-
Description
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See
Determines the number of clocks used for Flash
memory fetches (1 to 7 processor clocks).
Summary of Memory Acceleration Module registers
MAM Control Register (MAMCR - address 0xE01F C000) bit description
Value Description
00
01
10
11
-
Rev. 04 — 26 August 2009
Table
These bits determine the operating mode of the MAM.
MAM functions disabled
MAM functions partially enabled
MAM functions fully enabled
Reserved. Not to be used in the application.
Unused, always 0.
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
6–99.
Table
6–98. More detailed descriptions
Access Reset
R/W
R/W
value
0x0
0x07
UM10237
© NXP B.V. 2009. All rights reserved.
[1]
Address
0xE01F C000
0xE01F C004
Table
105 of 792
6–99.
Reset
value
0
0