LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 629

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
UM10237_4
User manual
6.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C,
0xE007 003C, 0xE007 403C)
The External Match Register provides both control and status of the external match pins.
In the descriptions below, “n” represents the Timer number, 0,1, 2, or 3, and “m” represent
a Match number, 0 through 3.
Table 552: External Match Register (T[0/1/2/3]EMR - addresses 0xE000 403C, 0xE000 803C,
Table 553. External Match Control
Bit
0
1
2
3
5:4
7:6
9:8
11:10 EMC3
15:12 -
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Symbol Description
EM0
EM1
EM2
EM3
EMC0
EMC1
EMC2
0xE007 003C, 0xE007 403C) bit description
00
01
10
11
External Match 0. When a match occurs between the TC and MR0, this
bit can either toggle, go low, go high, or do nothing, depending on bits 5:4
of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
External Match 1. When a match occurs between the TC and MR1, this
bit can either toggle, go low, go high, or do nothing, depending on bits 7:6
of this register. This bit can be driven onto a MATn.1 pin, in a
positive-logic manner (0 = low, 1 = high).
External Match 2. When a match occurs between the TC and MR2, this
bit can either toggle, go low, go high, or do nothing, depending on bits 9:8
of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
External Match 3. When a match occurs between the TC and MR3, this
bit can either toggle, go low, go high, or do nothing, depending on bits
11:10 of this register. This bit can be driven onto a MATn.0 pin, in a
positive-logic manner (0 = low, 1 = high).
External Match Control 0. Determines the functionality of External Match
0.
External Match Control 1. Determines the functionality of External Match
1.
External Match Control 2. Determines the functionality of External Match
2.
External Match Control 3. Determines the functionality of External Match
3.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Table 24–553
Table 24–553
Table 24–553
Table 24–553
Rev. 04 — 26 August 2009
Function
Do Nothing.
Clear the corresponding External Match bit/output to 0 (MATn.m pin is
LOW if pinned out).
Set the corresponding External Match bit/output to 1 (MATn.m pin is
HIGH if pinned out).
Toggle the corresponding External Match bit/output.
shows the encoding of these bits.
shows the encoding of these bits.
shows the encoding of these bits.
shows the encoding of these bits.
Chapter 24: LPC24XX Timer0/1/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
629 of 792
Reset
Value
0
0
0
0
00
00
00
00
NA