LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 477
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 421. Command Register (CAN1CMR - address 0xE004 4004, CAN2CMR - address 0xE004 8004) bit description
[1]
UM10237_4
User manual
Bit
0
1
2
3
4
5
6
7
[1][2]
[1][3]
[4]
[5]
[1][6]
- Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed in
case of an error or arbitration lost (single shot transmission).
- Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature.
No re-transmission will be performed in case of an error or arbitration lost.
- Setting the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR and AT. The
moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically.
- Setting TR and SRR simultaneously will ignore the set SRR bit.
Symbol Value
TR
AT
RRB
CDO
SRR
STB1
STB2
STB3
0 (absent)
1 (present)
0 (no action)
1 (present)
0 (no action)
1 (released)
0 (no action)
1 (clear)
0 (absent)
1 (present)
0 (not selected)
1 (selected)
0 (not selected)
1 (selected)
0 (not selected)
1 (selected)
Function
Transmission Request.
No transmission request.
The message, previously written to the CANxTFI, CANxTID, and
optionally the CANxTDA and CANxTDB registers, is queued for
transmission from the selected Transmit Buffer. If at two or all three
of STB1, STB2 and STB3 bits are selected when TR=1 is written,
Transmit Buffer will be selected based on the chosen priority
scheme (for details see
Abort Transmission.
Do not abort the transmission.
if not already in progress, a pending Transmission Request for the
selected Transmit Buffer is cancelled.
Release Receive Buffer.
Do not release the receive buffer.
The information in the Receive Buffer (consisting of CANxRFS,
CANxRID, and if applicable the CANxRDA and CANxRDB registers)
is released, and becomes eligible for replacement by the next
received frame. If the next received frame is not available, writing
this command clears the RBS bit in the Status Register(s).
Clear Data Overrun.
Do not clear the data overrun bit.
The Data Overrun bit in Status Register(s) is cleared.
Self Reception Request.
The message, previously written to the CANxTFS, CANxTID, and
optionally the CANxTDA and CANxTDB registers, is queued for
transmission from the selected Transmit Buffer and received
simultaneously. This differs from the TR bit above in that the receiver
is not disabled during the transmission, so that it receives the
message if its Identifier is recognized by the Acceptance Filter.
Select Tx Buffer 1.
Tx Buffer 1 is selected for transmission.
Select Tx Buffer 2.
Tx Buffer 2 is selected for transmission.
Select Tx Buffer 3.
Tx Buffer 3 is selected for transmission.
No self reception request.
Tx Buffer 1 is not selected for transmission.
Tx Buffer 2 is not selected for transmission.
Tx Buffer 3 is not selected for transmission.
Rev. 04 — 26 August 2009
Section 18–6.3 “Transmit Buffers
Chapter 18: LPC24XX CAN controllers CAN1/2
(TXB)”)
UM10237
© NXP B.V. 2009. All rights reserved.
0
Reset
Value
0
0
0
0
0
0
0
477 of 792
RM
Set
0
0
0
0
0
0
0
0
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