LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 38
![IC ARM7 MCU ROMLESS 208TFBGA](/photos/12/32/123248/mfg_lpc24xx_sml.jpg)
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 38.
UM10237_4
User manual
Bit
0
1
2
3
4
Symbol
GPIOM
EMC Reset
Disable
EMC Burst
Control
MCIPWR
Active
Level
OSCRANGE
System Controls and Status register (SCS - address 0xE01F C1A0) bit description
[1]
[1]
3.3.2.1 Examples of AHB2 settings
3.4.1 System Controls and Status register (SCS - 0xE01F C1A0)
3.4 Other system controls and status flags
Value Description
0
1
0
1
0
1
0
1
0
1
Table 36.
Table 37.
[1]
Some aspects of controlling LPC2400 operation that do not fit into peripheral or other
registers are grouped here.
Bit
13:12
17:16
Bit
13:12
17:16
Sequence based on round-robin.
GPIO access mode selection.
GPIO ports 0 and 1 are accessed via APB addresses in a fashion
compatible with previous LPC2000 devices.
High speed GPIO is enabled on ports 0 and 1, accessed via addresses in
the on-chip memory range. This mode includes the port masking feature
described in the GPIO chapter.
External Memory Controller Reset Disable.
Both EMC resets are asserted when any type of reset event occurs. In this
mode, all registers and functions of the EMC are initialized upon any reset
condition.
Many portions of the EMC are only reset by a power-on or brown-out event,
in order to allow the EMC to retain its state through a warm reset (external
reset or watchdog reset). If the EMC is configured correctly, auto-refresh can
be maintained through a warm reset.
External Memory Controller burst control (implemented on device revisions
C and higher).
Burst enabled.
Burst disabled.
MCIPWR pin control.
The MCIPWR pin is low.
The MCIPWR pin is high.
Main oscillator range select.
The frequency range of the main oscillator is 1 MHz to 20 MHz.
The frequency range of the main oscillator is 15 MHz to 25 MHz.
Symbol
EP1
EP2
Symbol
EP1
EP2
Priority sequence (bit 0 = 0): Ethernet, CPU
Priority sequence (bit 0 = 0): Ethernet, CPU
Description Priority value nn
CPU
Ethernet
Description Priority value nn
Ethernet
CPU
Rev. 04 — 26 August 2009
10 (2)
01 (1)
00
00
Chapter 3: LPC24XX System control
Priority sequence
1
2
Priority sequence
2
1
[1]
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
R/W
Access Reset
R/W
R/W
R/W
R/W
38 of 792
value
0
0
0
0
0
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