LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 417
![IC ARM7 MCU ROMLESS 208TFBGA](/photos/12/32/123248/mfg_lpc24xx_sml.jpg)
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
Fig 63. State transitions implemented in software during A-device switching from host to peripheral
no
bit in external OTG transceiver
clear BDIS_ACON_EN
discharge V
Note that only the subset of A-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.
Figure 15–63
but this is not necessary if the corresponding interrupt is enabled.
Following are code examples that show how the actions in
accomplished. The examples assume that ISP1302 is being used as the external OTG
transceiver.
a_wait_vfall
TMR set?
go to
yes
BUS
may appear to imply that the interrupt bits such as TMR should be polled,
when host sends SET_FEATURE
no
in external OTG transceiver
load and enable OTG timer
Rev. 04 — 26 August 2009
suspend host on port 1
set BDIS_ACON_EN
HNP_SUCCESS set?
with a_hnp_enable,
set A_HNP_TRACK
stop the OTG timer
a_peripheral
a_suspend
a_host
go to
go to
yes
Chapter 15: LPC24XX USB OTG controller
bit in external OTG transceiver
clear BDIS_ACON_EN
HNP_FAILURE set?
stop OTG timer
a_host
go to
Figure 15–63
yes
UM10237
no
© NXP B.V. 2009. All rights reserved.
are
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