LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 545

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
Table 470. SSP Register Map
[1]
UM10237_4
User manual
Generic Name
CR0
CR1
DR
SR
CPSR
IMSC
RIS
MIS
ICR
DMACR
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
6.1 SSPn Control Register 0 (SSP0CR0 - 0xE006 8000, SSP1CR0 - 0xE003
Description
Control Register 0. Selects the serial clock rate, bus
type, and data size.
Control Register 1. Selects master/slave and other
modes.
Data Register. Writes fill the transmit FIFO, and
reads empty the receive FIFO.
Status Register
Clock Prescale Register
Interrupt Mask Set and Clear Register
Raw Interrupt Status Register
Masked Interrupt Status Register
SSPICR Interrupt Clear Register
DMA Control Register
0000)
This register controls the basic operation of the SSP controller.
Rev. 04 — 26 August 2009
Chapter 20: LPC24XX SSP interface SSP0/1
Access Reset
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
NA
0
[1]
SSPn Register
Name & Address
SSP0CR0 - 0xE006 8000
SSP1CR0 - 0xE003 0000
SSP0CR1 - 0xE006 8004
SSP1CR1 - 0xE003 0004
SSP0DR - 0xE006 8008
SSP1DR - 0xE003 0008
SSP0SR - 0xE006 800C
SSP1SR - 0xE003 000C
SSP0CPSR - 0xE006 8010
SSP1CPSR - 0xE003 0010
SSP0IMSC - 0xE006 8014
SSP1IMSC - 0xE003 0014
SSP0RIS - 0xE006 8018
SSP1RIS - 0xE003 0018
SSP0MIS - 0xE006 801C
SSP1MIS - 0xE003 001C
SSP0ICR - 0xE006 8020
SSP1ICR - 0xE003 0020
SSP0DMACR - 0xE006 8024
SSP1DMACR - 0xE003 0024
UM10237
© NXP B.V. 2009. All rights reserved.
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