LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 423

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

1. Basic configuration
2. Features
3. Pin description
UM10237_4
User manual
The UART0/2/3 peripherals are configured using the following registers:
Table 376. UART0 Pin description
Pin
RXD0, RXD2, RXD3
TXD0, TXD2, TXD3
1. Power: In the PCONP register
2. Peripheral clock: In the PCLK_SEL0 register
3. Baud rate: In register U0/2/3LCR
4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR
5. Pins: Select UART pins and pin modes in registers PINSELn and PINMODEn (see
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR
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UM10237
Chapter 16: LPC24XX UART0/2/3
Rev. 04 — 26 August 2009
Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled
(PCUART2/3 = 0).
the PCLK_SEL1 register
access to registers DLL
rate. Also, if needed, set the fractional baud rate in the fractional divider register
(Table
enable FIFO.
Section
Remark: UART receive pins should not have pull-down resistors enabled.
(Table
enabled in the VIC using the VICIntEnable register
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
Built-in baud rate generator.
Fractional divider for baud rate control and mechanism that enables software flow
control implementation.
In addition, UART3 includes an IrDA mode to support infrared communication.
16–392).
16–386). This enables access to U0/2/3IER
9–5).
Rev. 04 — 26 August 2009
Type
Input
Output
(Table
(Table
Description
Serial Input. Serial receive data.
Serial Output. Serial transmit data.
(Table
16–380) and DLM
4–57), select PCLK_UART2/3.
(Table
4–63), set bits PCUART0/2/3.
16–386), set bit DLAB =1. This enables
(Table
(Table
(Table
(Table
4–56), select PCLK_UART0; in
16–381) for setting the baud
16–382). Interrupts are
7–106).
(Table
© NXP B.V. 2009. All rights reserved.
16–385) to
User manual
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