LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 565

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
UM10237_4
User manual
6.3 Argument Register (MCIArgument - 0xE008 C008)
6.4 Command Register (MCICommand - 0xE008 C00C)
Table 492: Clock Control register (MCIClock - address 0xE008 C004) bit description
While the MCI is in identification mode, the MCICLK frequency must be less than
400 kHz. The clock frequency can be changed to the maximum card bus frequency when
relative card addresses are assigned to all cards.
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
The MCIArgument register contains a 32 bit command argument, which is sent to a card
as part of a command message.
MCIArgument register.
Table 493: Argument register (MCIArgument - address 0xE008 C008) bit description
If a command contains an argument, it must be loaded into the argument register before
writing a command to the command register.
The MCICommand register contains the command index and command type bits:
Table 21–494
Bit
7:0
8
9
10
11
31:12
Bit
31:0
•
•
The command index is sent to a card as part of a command message.
The command type bits control the Command Path State Machine (CPSM). Writing 1
to the enable bit starts the command send operation, while clearing the bit disables
the CPSM.
Symbol
ClkDiv
Enable
PwrSave
Bypass
WideBus
-
Symbol
CmdArg
shows the bit assignment of the MCICommand register.
0
1
0
1
0
1
0
1
Value Description
Description
Command argument
Rev. 04 — 26 August 2009
MCI bus clock period:
Enable MCI bus clock:
Clock disabled.
Clock enabled.
Disable MCI clock output when bus is idle:
Always enabled.
Clock enabled when bus is active.
Disable bypass.
Enable bypass. MCLK driven to card bus output (MCICLK).
Enable wide bus mode:
Standard bus mode (only MCIDAT0 used).
Wide bus mode (MCIDAT3:0 used)
bits. The value read from a reserved bit is not defined.
MCLCLK frequency = MCLK / [2
Enable bypass of clock divide logic:
Reserved, user software should not write ones to reserved
Table 21–493
Chapter 21: LPC24XX SD/MMC card interface
shows the bit assignment of the
×
(ClkDiv+1)].
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0x0000 0000
565 of 792
Reset
Value
0x00
0
0
0
0
NA