LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 83

• Manufacturer Part Number: LPC2460FET208,551
• Description: IC ARM7 MCU ROMLESS 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2460FET208,551

• Program Memory Type: ROMless
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4260; 935283232551; LPC2460FET208-S

NXP Semiconductors
UM10237_4
User manual
10.8 Dynamic Memory Active to Precharge Command Period register
10.9 Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX
Table 74.
(EMCDynamictRAS - 0xFFE0 8034)
The EMCDynamicTRAS register enables you to program the active to precharge
command period, tRAS. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tRAS. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–75
Table 75.
- 0xFFE0 8038)
The EMCDynamicTSREX register enables you to program the self-refresh exit time,
tSREX. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tSREX, for devices without this parameter you
use the same value as tXSR. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selectsmust be programmed.
Table 5–76
Bit
3:0
31:4
Bit
3:0
31:4
Symbol
Precharge
command
period (tRP)
-
Symbol
Active to
precharge
command
period (tRAS)
-
Dynamic Memory Percentage Command Period register (EMCDynamictRP -
address 0xFFE0 8030) bit description
Dynamic Memory Active to Precharge Command Period register
(EMCDynamictRAS - address 0xFFE0 8034) bit description
shows the bit assignments for the EMCDynamicTRAS register.
shows the bit assignments for the EMCDynamicTSREX register.
Rev. 04 — 26 August 2009
0x0 -
0xE
0xF
0x0 -
0xE
0xF
Value Description
-
Value Description
-
Chapter 5: LPC24XX External Memory Controller (EMC)
n + 1 clock cycles. The delay is in EMCCLK cycles.
16 clock cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
n + 1 clock cycles. The delay is in EMCCLK cycles.
16 clock cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10237
© NXP B.V. 2009. All rights reserved.
83 of 792
Reset
Value
0x0F
NA
Reset
Value
0xF
NA