UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1057

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
21.5.2 Other requests
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Response and processing
(i) SET_INTERFACE() request
The following table shows how other requests are responded to and processed.
If wLength is other than the values shown in Table 21-3, if wIndex is other than the value set to the UF0 active
interface number register (UF0AIFN), or if wValue is other than the value set to the UF0 active alternative
setting register (UF0AAS), a STALL response is made in the status stage.
• Default state:
• Addressed state: A STALL response is made in the status stage when the SET_INTERFACE() request has
• Configured state: Null packet is transmitted in the status stage when the SET_INTERFACE() request has
When the SET_INTERFACE() request has been correctly processed, an interrupt is issued. All the Halt
Features of the endpoint linked to the target Interface are cleared after the SET_INTERFACE() request has
been cleared. The data toggle of all the endpoints related to the target Interface number is always initialized
again to DATA0. When the currently selected Alternative Setting is to be changed by correctly processing the
SET_INTERFACE() request, the FIFO of the endpoint that is affected is completely cleared, and all the related
interrupt sources are also initialized.
When the SET_INTERFACE() request has been completed, the FIFO of all the endpoints linked to the target
Interface are cleared. At the same time, Halt Feature and Data PID are initialized, and the related UF0 INT
status n register (UF0ISn) is cleared to 0 (n = 0 to 4). (Only Halt Feature and Data PID are cleared when the
SET_CONFIGURATION request has been completed.)
If the target Endpoint is not supported by the SET_INTERFACE() request during DMA transfer, the DMA
request signal is immediately deasserted, and the FIFO of the Endpoint that has been linked when the
SET_INTERFACE() request has been completed is completely cleared. As a result of this clearing of the FIFO,
data transferred by DMA is not correctly processed.
GET_DESCRIPTOR String
GET_STATUS Interface
CLEAR_FEATURE Interface
SET_FEATURE Interface
all SET_DESCRIPTOR
All other requests
Table 21-4. Response and Processing of Other Requests
A STALL response is made in the status stage when the SET_INTERFACE() request has
been received.
been received.
been received.
Request
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
Generation of CPUDEC interrupt request
Automatic STALL response
Automatic STALL response
Automatic STALL response
Generation of CPUDEC interrupt request
Generation of CPUDEC interrupt request
Response and Processing
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