UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 165
UPD70F3765GF-GAT-AX
Manufacturer Part Number
UPD70F3765GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3765GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3765GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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P50
P51
P52
P53
P54
Pin Name
Note V850ES/JG3-H only
Note
Note
Note
TIAB01
KR0
TOAB01
RTP00
UDMARQ1
TIAB02
KR1
TOAB02
RTP01
UDMAAK1
TIAB03
KR2
TOAB03
RTP02
SIF2
TIAB00
KR3
TOAB00
RTP03
SOF2
KR4
RTP04
Alternate Function
Name
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
I/O
P50 = Setting not required
P50 = Setting not required
P50 = Setting not required
P50 = Setting not required
P50 = Setting not required
P51 = Setting not required
P51 = Setting not required
P51 = Setting not required
P51 = Setting not required
P51 = Setting not required
P52 = Setting not required
P52 = Setting not required
P52 = Setting not required
P52 = Setting not required
P53 = Setting not required
P53 = Setting not required
P53 = Setting not required
P53 = Setting not required
P53 = Setting not required
P54 = Setting not required
P54 = Setting not required
P54 = Setting not required
Pn Register
Pnx Bit of
PM50 = Setting not required PMC50 = 1
PM50 = Setting not required PMC50 = 1
PM50 = Setting not required PMC50 = 1
PM50 = Setting not required PMC50 = 1
PM50 = Setting not required PMC50 = 1
PM51 = Setting not required PMC51 = 1
PM51 = Setting not required PMC51 = 1
PM51 = Setting not required PMC51 = 1
PM51 = Setting not required PMC51 = 1
PM51 = Setting not required PMC51 = 1
PM52 = Setting not required PMC52 = 1
PM52 = Setting not required PMC52 = 1
PM52 = Setting not required PMC52 = 1
PM52 = Setting not required PMC52 = 1
PM53 = Setting not required PMC53 = 1
PM53 = Setting not required PMC53 = 1
PM53 = Setting not required PMC53 = 1
PM53 = Setting not required PMC53 = 1
PM53 = Setting not required PMC53 = 1
PM54 = Setting not required PMC54 = 1
PM54 = Setting not required PMC54 = 1
PM54 = Setting not required PMC54 = 1
Table 4-20. Using Port Pin as Alternate-Function Pin (4/10)
PMn Register
PMnx Bit of
PMCn Register
PMCnx Bit of
PFCE50 = 0
PFCE50 = 0
PFCE50 = 0
PFCE50 = 1
PFCE50 = 1
PFCE51 = 0
PFCE51 = 0
PFCE51 = 0
PFCE51 = 1
PFCE51 = 1
PFCE52 = 0
PFCE52 = 0
PFCE52 = 0
PFCE52 = 1
PFCE53 = 0
PFCE53 = 0
PFCE53 = 0
PFCE53 = 1
PFCE53 = 1
PFCE54 = 0
PFCE54 = 0
PFCE54 = 1
PFCEn Register
PFCEnx Bit of
PFC50 = 0
PFC50 = 0
PFC50 = 1
PFC50 = 0
PFC50 = 1
PFC51 = 0
PFC51 = 0
PFC51 = 1
PFC51 = 0
PFC51 = 1
PFC52 = 0
PFC52 = 0
PFC52 = 1
PFC52 = 0
PFC53 = 0
PFC53 = 1
PFC53 = 1
PFC53 = 0
PFC53 = 1
PFC54 = 0
PFC54 = 1
PFC54 = 0
PFCn Register
PFCnx Bit of
KRM0 (KRM)= 0
TAB0TIG2, TAB0TIG3 (TAB0IOC1) = 0
KRM1 (KRM) = 0
TAB0TIG4, TAB0TIG5 (TAB0IOC1) = 0
KRM2 (KRM) = 0
TAB0TIG6, TAB0TIG7 (TAB0I0C1) = 0
KRM3 (KRM) = 0
TAB0TIG0, TAB0TIG1 (TAB0IOC1) = 0,
TAB0EES0, TAB0EES1 (TAB0IOC2) = 0,
TAB0ETS0, TAB0ETS1 (TAB0IOC2) = 0
(Registers)
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