UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 720

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
17.1 Features
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The V850ES/JG3-H and V850ES/JH3-H have a 5-channel UARTC.
Transfer rate: 300 bps to 3 Mbps (using internal system clock of 24 MHz and dedicated baud rate generator)
Full-duplex communication: Internal UARTCn receive data register (UCnRX)
2-pin configuration:
Reception error detection function
• Parity error
• Framing error
• Overrun error
Interrupt sources: 2 types
• Reception completion interrupt (INTUCnR):
• Transmission enable interrupt (INTUCnT):
Character length: 7 to 9 bits
Parity function: Odd, even, 0, none
Transmission stop bit: 1, 2 bits
On-chip dedicated baud rate generator
MSB-/LSB-first transfer selectable
Transmit/receive data inverted input/output possible
SBF (Sync Break Field) transmission in the LIN (Local Interconnect Network) communication format
• 13 to 20 bits selectable for the SBF transmission
• Recognition of 11 bits or more possible for SBF reception
• SBF reception flag provided
Remark
n = 0 to 4
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Internal UARTCn transmit data register (UCnTX)
TXDCn: Transmit data output pin
RXDCn: Receive data input pin
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
This interrupt occurs upon transfer of receive data from the receive
shift register to the receive data register after serial transfer is
complete, in the reception enabled status.
This interrupt occurs upon transfer of transmit data from the
transmit data register to the transmit shift register in the
transmission enabled status.
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