UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 210

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Clock control register (CKC)
Caution 1.
Remark Both the CPU clock and peripheral clock are divided by the CKC register, but only the CPU clock is
The CKC register is a special register. Data can be written to this register only in a combination of specific
sequence (see 3.4.8 Special registers).
The CKC register controls the internal system clock in the PLL mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 0AH.
2.
divided by the PCC register.
After reset:
Be sure to set the CKC register to 0BH. When setting this register to a value other than
CKC
0BH or leaving it set to its initial value without setting it to 0BH, enabling PLL operation
(PLLCTL.SELPLL = 1) is prohibited.
Be sure to set bits 3 and 1 to ‘‘1’’ and clear bits 7 to 4 and 2 to ‘‘0’’.
CKDIV0
0AH
0
1
0
Setting prohibited
f
XX
R/W
= 8 × f
0
X
(f
Address:
Internal system clock (f
X
= 3.0 to 6.0 MHz)
0
FFFFF822H
0
CHAPTER 6 CLOCK GENERATION FUNCTION
XX
1
) in PLL mode
0
1
CKDIV0
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