UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 394

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
PWM waveform from the TOABnk pin.
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bit counter matches
the value of the CCRk buffer register.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TABnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TABnCCRm register while the counter is operating. The newly
The compare match interrupt request signal (INTTABnCC0) is generated when the 16-bit counter counts up next time
Remark
TABnCTL0
TABnCTL1
Active level width = (Set value of TABnCCRk register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1)
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark
k = 1 to 3,
m = 0 to 3,
n = 0, 1
TABnSYE
TABnCE
0/1
0
n = 0, 1
TABnEST
0
0
Figure 8-26. Setting of Registers in PWM Output Mode (1/3)
TABnEEE
0/1
0
0
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0
0
TABnCKS2 TABnCKS1 TABnCKS0
TABnMD2 TABnMD1 TABnMD0
0/1
1
0/1
0
0/1
0
1, 0, 0:
PWM output mode
0: Operate on count clock
1: Count by external event
Select count clock
0: Stop counting
1: Enable counting
selected by TABnCKS0 to
TABnCKS2 bits
count input signal
Page 394 of 1509
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