UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 870

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
19.13 Wakeup Function
extension code has been received by using the slave function of the I
efficient by preventing unnecessary INTIICn signals from occurring when addresses do not match.
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which generated
the start condition) to a slave device.
determines whether INTIICn signal is enabled or disabled (n = 0 to 2).
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Notes 1.
The makeup function is a function that generates an interrupt request signal (INTIICn) when a local address or
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
However, when a stop condition is detected, the IICCn.SPIEn bit is set regardless of the wakeup function, and this
Transmitting address transmission
Read/write data after address transmission
Transmitting extension code
Read/write data after extension code transmission
Transmitting data
ACK transfer period after data reception
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When SDA0n pin is low level while attempting to generate
restart condition
When stop condition is detected while attempting to
generate restart condition
When DSA0n pin is low level while attempting to generate
stop condition
When SCL0n pin is low level while attempting to generate
restart condition
2.
When the IICCn.WTIMn bit = 1, an INTIICn signal occurs at the falling edge of the ninth clock. When the
WTIMn bit = 0 and the extension code’s slave address is received, an INTIICn signal occurs at the falling
edge of the eighth clock (n = 0 to 2).
When there is a possibility that arbitration will occur, set the SPIEn bit to 1 for master device operation (n =
0 to 2).
Table 19-5. Status During Arbitration and Interrupt Request Signal Generation Timing
Status During Arbitration
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when IICCn.SPIEn bit = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when IICCn.SPIEn bit = 1)
At falling edge of eighth or ninth clock following byte transfer
Interrupt Request Generation Timing
2
C bus. This function makes processing more
CHAPTER 19 I
Page 870 of 1509
Note 1
Note 1
Note 1
Note 2
Note 2
2
C BUS