UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 587

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
HZA0CTLn
(n = 0, 1)
After reset: 00H
HZA0DCEn
HZA0DCMn
HZA0DCEn
HZA0DCNn
Rewrite the HZA0DCMn bit when the HZA0DCEn bit = 0.
• Rewrite the HZA0DCNn and HZA0DCPn bits when the HZA0DCEn bit is 0.
• For the valid edge specification of the interrupts of the INTP09 and INTP16 pins,
•
• High-impedance output control is performed when the valid edge is input after the
see 23.6.2 (3) External interrupt falling, rising edge specification register 3
(INTR3, INTF3) and (6) External interrupt falling, rising edge specification
For the edge specification of the external pins, begin with the TOAB1OFF and
TOAA1OFF pins. Then, perform edge specification for the external pins other than
the TOAB1OFF and TOAA1OFF pins. Otherwise, an undefined edge may be
detected when the edge for the TOAB1OFF and TOAA1OFF pins is specified.
operation is enabled (by setting HZA0DCEn bit to 1). If the external pin is at
the active level when the operation is enabled, therefore, high-impedance output
control is not performed.
register 9H (INTR9, INTF9).
<7>
0
1
0
1
0
0
1
1
R/W
HZA0DCMn HZA0DCNn HZA0DCPn HZA0DCTn HZA0DCCn
Disable high-impedance output control operation. Pins can function as
output pins.
Enable high-impedance output control operation.
Setting of the HZA0DCCn bit is valid regardless of the external pin input.
Setting of the HZA0DCCn bit is invalid while the external pin input holds a
level detected as abnormal (active level).
HZA0DCPn
<6>
0
1
0
1
Condition of clearing high-impedance state by HZA0DCCn bit
Address: HZA0CTL0 FFFFF590H, HZA0CTL1 FFFFF591H
No valid edge (setting the HZA0DCFn bit by external pin input
is prohibited).
Rising edge of the external pin is valid
(abnormality is detected by rising edge input).
Falling edge of the external pin is valid
(abnormality is detected by falling edge input).
Setting prohibited
5
High-impedance output control
External pin input edge specification
4
CHAPTER 11 MOTOR CONTROL FUNCTION
<3>
<2>
1
0
HZA0DCFn
<0>
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