UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 743

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
17.6.3 SBF transmission
transmission is started by setting (to 1) the SBF transmission trigger (UCnOPT0.UCnSTT bit).
output. A transmission enable interrupt request signal (INTUCnT) is generated upon SBF transmission start. Following
the end of SBF transmission, the UCnSTT bit is automatically cleared. Thereafter, the UART transmission mode is
restored.
transmission trigger (UCnSTT bit) is set.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnTXE bit = 1, the transmission enabled status is entered, and SBF
Thereafter, a low level the width of bits 13 to 20 specified by the UCnOPT0.UCnSLS2 to UCnOPT0.UCnSLS0 bits is
Transmission is suspended until the data to be transmitted next is written to the UCnTX register, or until the SBF
TXDCn
INTUCnT
interrupt
Setting of UCnSTT bit
1
2
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Figure 17-10. SBF Transmission
3
4
5
6
7
8
9
10
11
12
13
Stop
bit
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