UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 837
UPD70F3765GF-GAT-AX
Manufacturer Part Number
UPD70F3765GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3765GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3765GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
19.5 I
19.5.1 Pin configuration
resistor is required.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows (n = 0 to 2).
SCL0n .................This pin is used for serial clock input and output.
SDA0n ................This pin is used for serial data input and output.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
2
C Bus Mode Functions
(Clock input)
Clock output
Data output
Data input
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Master device
Figure 19-6. Pin Configuration Diagram
SCL0n
SDA0n
V
V
DD
DD
SDA0n
SCL0n
Slave device
CHAPTER 19 I
(Clock output)
Clock input
Data output
Data input
Page 837 of 1509
2
C BUS
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