UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 669

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
13.3 Registers
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Watchdog timer mode register 2 (WDTM2)
Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 13-2 Watchdog Timer 2 Clock
Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.9 (2)
The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
This register can be read or written in 8-bit units. This register can be read any number of times, but it can be
written only once following reset release.
Reset sets this register to 67H.
2. Although watchdog timer 2 can be stopped just by stopping operation of the internal
3. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly generated
4. To intentionally generate an overflow signal, write data to the WDTM2 register twice, or
5. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop the
WDTM2
Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
Selection.
oscillator, clear the WDTM2 register to 00H to securely stop the timer (to avoid selection of
the main clock or subclock due to an erroneous write operation).
and the counter is reset.
write a value other than “ACH” to the WDTE register once.
However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal
is not generated even if data is written to the WDTM2 register twice, or a value other than
“ACH” is written to the WDTE register once.
internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP bit cannot be
set to 1, set the WDCS23 bit to 1 (2
IDLE1, IDLW2, sub-IDLE, and subclock operation modes).
After reset: 67H
WDM21
0
0
1
0
WDM20
WDM21
R/W
0
1
–
Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
(generation of INTWDT2 signal)
Reset mode (generation of WDT2RES signal)
WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Selection of operation mode of watchdog timer 2
CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
n
/f
XX
is selected and the clock can be stopped in the
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