UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1141

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(8) UF0 bulk-out 2 length register (UF0BO2L)
(9) UF0 bulk-in 1 register (UF0BI1)
UF0BO2L
UF0BI1
The UF0BO2L register stores the length of the data held by the UF0BO2 register.
This register is read-only, in 8-bit units. A write access to this register is ignored.
The UF0BO2L register always updates the received data length while it is receiving data. If the final transfer is
abnormal reception, the UF0BO2L register is cleared to 00H, and an interrupt request is not generated. Only if the
reception is normal, the interrupt request is generated, and FW can read as much data from the UF0BO2 register
as the value read from the UF0BO2L register. The value of the UF0BO2L register is decremented each time the
UF0BO2 register has been read.
The UF0BI1 register is a 64-byte × 2 FIFO that stores data for Endpoint1. This register consists of two banks of 64-
byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU
sides. The toggle operation takes place when no data is in the FIFO on the SIE side (counter value = 0) and when
the FIFO on the CPU side is correctly written (FIFO full or BKI1DED bit = 1).
This register is write-only, in 8-bit units. When this register is read, 00H is read.
The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint1 only when the
BKI1NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). The address at which data is to be
written or read is managed by the hardware. Therefore, FW can transmit data to the host only by writing the data to
the UF0BI1 register sequentially. A short packet is transmitted when data is written to the UF0BI1 register and the
BKI1DED bit of the UF0DEND register is set to 1 (BKIN1 bit of UF0EPS0 register = 1 (data exists)). A Null packet
is transmitted when the UF0BI1 register is cleared and the BKI1DED bit of the UF0DEND register is set to 1
(BKIN1 bit of the UF0EPS0 register = 1 (data exists)). When the data is transmitted correctly, a FIFO toggle
operation occurs. The BKI1DT bit of the UF0IS2 register is set to 1, and an interrupt request is generated for the
CPU. An interrupt request or DMA request can be selected by using the DQBI1MS bit of the UF0IDR register.
The operation of the UF0BI1 register is illustrated below.
Bit position
Bit position
7 to 0
7 to 0
BKI17
BKO2L7
7
7
BKO2L7 to
BKO2L0
BKI17 to BKI10 These bits store data for Endpoint1.
Bit name
Bit name
BKI16
BKO2L6
6
6
BKI15
BKO2L5
These bits store the length of the data held by the UF0BO2 register.
5
5
BKO2L4
BKI14
4
4
BKO2L3
BKI13
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
3
BKO2L2
BKI12
2
2
Function
Function
BKO2L1
BKI11
1
1
BKI10
BKO2L0
0
0
00200110H
0020010EH
Address
Address
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After reset
Undefined
After reset
00H