UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 182

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
5.4.3
bit units. The bus size is as follows.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The V850ES/JG3-H and V850ES/JH3-H access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-
• The bus size of the on-chip peripheral I/O is fixed to 16 bits.
• The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register).
The operation when each of the above is accessed is described below. All data is accessed starting from the lower side.
The V850ES/JG3-H and V850ES/JH3-H support only the little-endian format.
(1) Data space
The V850ES/JG3-H and V850ES/JH3-H have an address misalign function.
With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword
data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least
twice, causing the bus efficiency to drop.
(a) Halfword-length data access
(b) Word-length data access
Access by bus size
A byte-length bus cycle is generated twice if the least significant bit of the address is 1.
(i) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if
(ii) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
the least significant bit of the address is 1.
31
000BH
0007H
0003H
Figure 5-2. Little-Endian Address in Word
24 23
000AH
0006H
0002H
16 15
0009H
0005H
0001H
CHAPTER 5 BUS CONTROL FUNCTION
8 7
0008H
0004H
0000H
0
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