UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 363

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(e) TABn counter read buffer register (TABnCNT)
(f) TABn capture/compare register 0 (TABnCCR0)
(g) TABn capture/compare registers 1 to 3 (TABnCCR1 to TABnCCR3)
The count value of the 16-bit counter can be read by reading the TABnCNT register.
If D
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode.
Therefore, mask the interrupt signals by using the interrupt mask flags (TABnCCMK1 to
request signal (INTTABnCC0) is generated when the number of external event counts reaches
(D
However, the set value of the TABnCCR1 to TABnCCR3 registers are transferred to the CCR1 to
CCR3 buffer registers. When the count value of the 16-bit counter matches the value of the
CCR1 to CCR3 buffer registers, compare match interrupt request signals (INTTABnCC1 to
INTTABnCC3) are generated.
TABnCCMK3).
Caution
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are
0
0
+ 1).
is set to the TABnCCR0 register, the counter is cleared and a compare match interrupt
Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2)
For TAB0, when an external clock is used as the count clock, the external clock can be input
only from the TIAB00 pin. At this time, set the TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0
bits to 00 (capture trigger input (TIAB00 pin): no edge detection).
2. n = 0, 1
not used in the external event count mode.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
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